Hardware Architectures for Post-Quantum Cryptography – Key Generator for the Niederreiter Cryptosystem

26.10.2017 16:30-18:00

Hardware Architectures for Post-Quantum Cryptography – Key Generator for the Niederreiter Cryptosystem

26.10.2017, 16:30 – 18:00

Speaker: Wen Wang, Yale University | Location: Mornewegstraße 32 (S4|14), Room 3.1.01, Darmstadt

Organizer: Denis Butin

Abstract

Whether due to advances in classical cryptanalysis methods, or the advent of quantum computing, there is immediate need to prototype and evaluate the post-quantum cryptography (PQC) algorithms that can ensure long-term security of our data and communication. This talk will present a post-quantum secure, efficient, and tunable FPGA implementation of the key generation algorithm for the Niederreiter cryptosystem using binary Goppa codes. Our key generator implementation requires as few as 896,052 cycles to produce both public and private portions of a key, and can achieve an estimated frequency Fmax of over 240 MHz when synthesized for Stratix V FPGAs.

This work is the first hardware-based implementation that works with parameters exceeding the recommended 128-bit post-quantum security level. The key generator can produce a key pair for parameters m = 13, t = 119 and n = 6960 in only 3.7 ms when no systemization failure occurs. To achieve such performance, we implemented an optimized and parameterized Gaussian systemizer for matrix systemization, which works for any large-sized matrix over any binary field GF(2m). We presented the first FPGA-based implementation of the Gao-Mateer additive FFT, which only takes about 1000 clock cycles to finish the evaluation of a degree-119 polynomial at 213 data points. The hardware design principles, performance, energy and resource needs of these main modules and the whole key generator will be presented in this talk.

Short Bio

Wen Wang, a Ph. D. candidate in the Department of Electrical Engineering at Yale University, working with Prof. Jakub Szefer. Recently I have been working on the hardware (FPGA) implementation of post-quantum secure cryptographic algorithms.

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