Organizer: Alexandra Weber (TU Darmstadt/CROSSING)
Detailed microarchitectural models are necessary to predict, explain, or optimize the performance of software running on modern microprocessors. Building such models often requires a significant manual effort, as the documentation provided by hardware manufacturers is typically not precise enough. In this talk, we will look at techniques for generating models of microarchitectures automatically.
First, I will present nanoBench (https://github.com/andreas-abel/nanoBench), which is a tool for evaluating small microbenchmarks using hardware performance counters on Intel and AMD x86 systems. Unlike previous tools, nanoBench can execute microbenchmarks directly in kernel space. This makes it possible to benchmark privileged instructions, and it enables more accurate measurements. The reading of the performance counters is implemented with minimal overhead, avoiding functions calls and branches.
In the second part of the talk, I will describe techniques to automatically generate microbenchmarks for haracterizing cache architectures and for determining the latency, throughput, and port usage of more than 13,000 instruction variants. We have applied these techniques to 17 different Intel and AMD microarchitectures; the results are available on our website www.uops.info.
- Zoom Details: Meeting ID: 818 4273 7559, Passcode: 837893